Mastering Clock Constraints: A Deep Dive into create_clock and create_generate_clock in SDC
In the world of digital design, especially when dealing with complex integrated circuits, precise timing is paramount. Static Timing Analysis (STA) relies heavily on accurate clock definitions to ensure that signals propagate correctly and meet timing requirements. System Design Constraints (SDC) provide the language for communicating these timing specifications to synthesis and STA tools. Today, we'll dive into two fundamental SDC commands: create_clock and create_generate_clock.
Understanding the Foundation: create_clock
The create_clock command is your primary tool for defining the fundamental clocks in your design. Think of these as the "master" clocks that drive your system's operations.
Purpose:
create_clock establishes a clock object with defined characteristics like its period and waveform. This information is critical for:
* Timing Analysis: Allowing STA tools to accurately calculate signal delays and identify timing violations.
* Clock Network Optimization: Guiding synthesis and place-and-route tools to build efficient clock trees.
* Timing Graph Construction: Forming the basis for analyzing all timing paths in the design.
Key Parameters:
-period <period_value> (Required): This is the most crucial parameter, specifying the clock's period in nanoseconds (ns). For example, -period 10 defines a clock with a 10 ns period (100 MHz frequency).-waveform {<rise_time> <fall_time>} (Optional): This defines the exact timing of the clock's rising and falling edges within its period, also in nanoseconds. The default is a 50% duty cycle, meaning a rising edge at 0.0 ns and a falling edge at period_value / 2 ns. You can specify asymmetrical duty cycles here. For instance, -waveform {0 3} on a 10 ns clock means it rises at 0 ns and falls at 3 ns.<source> (Optional, but common): This specifies the physical port or pin in your design where this clock originates. You'll often see it used with commands like [get_ports CLK_IN] or [get_pins U1/CLK_PIN].-name <clock_name> (Optional, but essential for virtual clocks): Assigns a custom name to the clock. This name is used in subsequent SDC commands. When defining a "virtual clock" (one not physically present in the design but used for external interface timing), -name is used, and <source> is omitted.-add (Optional): Use this if a source already has a clock defined, and you want to add another clock to it.
Example:
# Define a 10ns clock on the input port CLK_IN
create_clock -period 10 [get_ports CLK_IN]
# Define a 6ns clock with a specific waveform on port SYS_CLK_PORT
create_clock -period 6 -waveform {0 3} [get_ports SYS_CLK_PORT]
# Define a virtual clock named EXT_REF_CLK with a 5ns period
create_clock -period 5 -name EXT_REF_CLK
Derived Clocks: create_generated_clock
In modern designs, clocks are rarely just simple square waves. They often go through Phase-Locked Loops (PLLs), clock dividers, multipliers, or multiplexers, creating derived or "generated" clocks. The create_generated_clock command is how you tell the STA tool about these derived clocks.
Purpose:
This command defines a clock whose timing is related to an existing master clock. STA tools use this information to understand the timing relationships between different clock domains, which is critical for analyzing clock domain crossings (CDCs) and ensuring overall design integrity.
Key Parameters and Concepts:
-
-master_clock <clock>:
- What it means: When a pin receives multiple clocks (e.g., through a multiplexer), you might need to explicitly tell SDC which master clock is active for a particular generated clock. This parameter specifies that master clock.
- When to use: Essential when a
-source pin has more than one clock feeding into it, and you want to define a generated clock derived from a specific master clock among them. Often used with -add to define multiple generated clocks from the same source pin, each tied to a different master.
- Example:
tcl
# Assume mux_out_pin can be driven by CLK_A or CLK_B
create_generated_clock -name gen_clk_A -source [get_pins mux_out_pin] -master_clock CLK_A [get_pins FF1/Q]
create_generated_clock -name gen_clk_B -source [get_pins mux_out_pin] -master_clock CLK_B -add [get_pins FF1/Q]
-
-edges <edge_list>:
- What it means: This is a sophisticated way to define the generated clock's waveform by mapping specific edges of the master clock to the rising and falling edges of the generated clock. The master clock edges are numbered sequentially (1st rising, 1st falling, 2nd rising, 2nd falling, etc.).
- Format:
{master_rising_edge_for_gen_rise master_edge_for_gen_fall master_edge_for_next_gen_rise}.
- When to use: Ideal for complex clocking schemes where simple division/multiplication doesn't suffice, or when you need fine-grained control over the generated clock's pulse shape relative to the master. This parameter often cannot be used with
-divide_by or -multiply_by.
- Example (Clock Division by 2):
Imagine a master CLK with edges at 0ns (R1), 5ns (F1), 10ns (R2), 15ns (F2), 20ns (R3), etc.
tcl
# Master clock CLK has edges: 1(0ns R), 2(5ns F), 3(10ns R), 4(15ns F), 5(20ns R)...
create_generated_clock -name clk_div2_edge -source [get_ports CLK] -edges {1 3 5} [get_pins FF1/Q]
This generates a clock at FF1/Q that rises with master edge 1 (0ns), falls with master edge 3 (10ns), and rises again with master edge 5 (20ns). This effectively creates a clock with twice the period (half the frequency) of the master.
-
-divide_by <factor>:
- What it means: This is a straightforward way to create a slower clock. The generated clock's frequency will be the master clock's frequency divided by
<factor>. Consequently, its period will be <factor> times the master clock's period.
- When to use: When you need a clock that runs at a simple fraction of the master clock's speed.
- Example:
tcl
create_clock -name CLK_SYS -period 10 [get_ports clk_in]
# Create a clock that is half the frequency of CLK_SYS
create_generated_clock -name CLK_DIV_2 -source [get_pins clk_in] -divide_by 2 [get_pins reg_div_2/Q]
This results in CLK_DIV_2 having a 20 ns period.
-
-multiply_by <factor>:
- What it means: This creates a faster clock. The generated clock's frequency will be the master clock's frequency multiplied by
<factor>, meaning its period is the master clock's period divided by <factor>.
- When to use: For generating higher-frequency clocks, common with PLLs or frequency synthesizers.
- Example:
tcl
create_clock -name CLK_MASTER -period 10 [get_ports clk_in]
# Create a clock that is twice the frequency of CLK_MASTER
create_generated_clock -name CLK_MUL_2 -source [get_pins clk_in] -multiply_by 2 [get_pins pll_out_pin]
This generates CLK_MUL_2 with a 5 ns period.
-
-duty_cycle <percent>:
- What it means: Sets the duty cycle of the generated clock to a specified percentage (0.0 to 100.0). The default is usually 50%.
- When to use: To define clocks with non-50% duty cycles, which is particularly relevant when using
-multiply_by or when the clock generation logic (like a PLL or clock divider circuit) is configured to produce a specific pulse width.
- Example:
tcl
create_clock -name CLK_IN -period 10 [get_ports clk_in]
# Generate a clock with double the frequency and a 25% duty cycle
create_generated_clock -name CLK_MUL_2_DC -source [get_ports clk_in] -multiply_by 2 -duty_cycle 25 [get_pins pll_out_pin]
This creates a clock that is twice as fast as CLK_IN but has a narrower pulse width (25% of its period).
Combining Parameters for Complex Clocks
Many clocking scenarios involve both frequency multiplication/division and specific edge alignments. SDC tools often allow combining these parameters.
Example (Fractional Clock Generation for PLLs):
PLLs and MMCMs frequently generate clocks with fractional frequency relationships.
# Assume CLKIN is the master clock at pin mmcm0/CLKIN
# We want to generate CLKOUT at pin mmcm0/CLKOUT
# which is 4/3 times the frequency of CLKIN.
create_generated_clock -name clk_4_3_ratio \
-source [get_pins mmcm0/CLKIN] \
-multiply_by 4 \
-divide_by 3 \
[get_pins mmcm0/CLKOUT]
This command elegantly defines a clock clk_4_3_ratio at mmcm0/CLKOUT that is precisely 4/3 times the frequency of the master clock at mmcm0/CLKIN, a common scenario for clock synthesizers.
By mastering create_clock and create_generated_clock, you gain precise control over your design's timing, ensuring your digital systems operate as intended.
References
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